Creonic develops IP cores as ready-for-use solutions for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. Our products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance.
LDPC and Turbo Coding
DVB-RCS2 Turbo Decoder
Our BCH / Viterbi encoder and
decoder solutions can be adapted to
different block lengths, code rates,
and throughput requirements.
We offer architectures for different throughput requirements and modulation schemes, such as QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM.
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We offer floating point and bit-accurate software models of our IP cores as standalone solutions. Learn more...