LDPC decoder and turbo decoder for FPGA and ASICCreonic develops IP cores as ready-for-use solutions for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. Our products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance.

 

 

LDPC and Turbo Coding

DVB-RCS2 Turbo Decoder
DVB-S2 LDPC Encoder/Decoder
DVB-C2 LDPC Decoder
IEEE 802.11ad (WiGig) LDPC Decoder
IEEE 802.11 (WiFi) LDPC Decoder
IEEE 802.15.3c (60 GHz PHY) LDPC Decoder
GEO-Mobile Radio (GMR) LDPC Decoder
1 Gbit/s LDPC Encoder/Decoder (WiMedia UWB)

 We offer

  • the design of LDPC/Turbo encoder and decoder for any standard,
  • the adaptation of existing solutions to your needs, and
  • the design of proprietary LDPC and Turbo codes.

Coding (Miscellaneous)

Parametrizable Open Source Viterbi Decoder

DVB-S2 BCH Encoder/Decoder

DVB-C2 BCH EncoderDecoder

Our BCH / Viterbi encoder and

decoder solutions can be adapted to

different block lengths, code rates,

and throughput requirements.

MIMO

MMSE MIMO Detector

 

Soft-Decision Demapping

We offer architectures for different throughput requirements and modulation schemes, such as QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM.

Contact us to learn more!

 

Software IP

We offer floating point and bit-accurate software models of our IP cores as standalone solutions. Learn more...

TPL_BEEZ2_ADDITIONAL_INFORMATION