CCSDS 231.0-B-3 LDPC Encoder and Decoder IP Core from Creonic Now Available
Kaiserslautern, Germany, May 6, 2021 — Creonic GmbH, a leading IP core provider in the communications market, announced today the release of their new CCSDS 231.0-B-3 LDPC Encoder and Decoder IP cores for the satellite market. The IP cores complement the company’s broadest product portfolio of LDPC IP cores on the market.
The CCSDS 231.0-B-3 LDPC codes with rates of 1/2 and uncoded block lengths of 64 and 256 bits are specially designed for telecommand (TC) and free space optical applications. Encoder and decoder IP support the LDPC coding schemes as defined by the CCSDS 231.0-B-3 or the 142.0-B-1 versions of the standard.
The IP Cores are available for ASIC and FPGA (Xilinx and Intel) technologies either as VHDL source code or encrypted source code. In addition, the cores come with HDL simulation models, VHDL testbench, bit accurate Matlab, C or C++ simulation model and comprehensive documentation.
For more information, please visit the product page or contact us.
Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC, Turbo, Polar), modulation, and synchronization. The company offers the richest product portfolio in this field, covering standards like 5G, 4G, DVB-S2X, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit our website at www.creonic.com.
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