About Creonic

Creonic stands for highest standards in quality, state-of-the-art technology and simple integration under adherence to time limits and budgets. Our products and services comply with the highest requirements with respect to quality and performance.

CRE ative microelectr ONIC s

Creonic GmbH is an ISO 9001:2015 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC, Turbo, Polar), modulation, and synchronization. Creonic implements FPGA and ASIC designs for wireless and wired communication. This includes a variety of communication standards, such as DVB-S2X, DVB-RCS2, 5G, 4G, CCSDS, DOCSIS, WiFi, WiGig, and UWB. Chip designs for optical communication are also available, enabling inter satellite link (ISL) communication. 
As the richest in this field, the IP core product portfolio is used by dozens of customers worldwide in satellite modems and satellites. With Creonic’s chip designs, companies from start-ups to global corporations can realize their NewSpace goals.



The decision to found the company is made.


Registration of the trademark Creonic in the trademark register.

Birth of Creonic UG (haftungsbeschränkt) by signing the shareholder's agreement.

Award as founders of the year 2010.


Change of name to Creonic GmbH.


Participation in first research project (ESR Projekt, BMBF).


Successful ISO 9001:2008 Certification as the only IP vendor for FEC Cores with certification.

Creonic becomes part of the Xilinx Alliance Partner Program.


Participation in German Silicon Valley Accelerator.

Creonic joins the DVB Project.

Inclusion in Altera Partner Program.

Introduction of the DVB-S2X Demodulator and Decoder


The Creonic team is getting bigger: time to move to larger premises.


Introduction of the DVB-S2X Wideband Demodulator and Decoder


Successful upgrade to ISO 9001:2015.​


Establishment of our own laboratory.


Creonic Joins German Center for Satellite Communications (DeSK).

10 years of Creonic.


Creonic's new  DVB-GSE Encapsulator and Decapsulator IP cores are now available.

Launch of Creonic's CCSDS 231.0-B-3 LDPC Encoder and Decoder IP cores.


Release of Creonic's DVB-RCS2 Multi-Carrier Receiver.

Creonic joins New Space Initiative.


Introduction of Creonic's DVB-GSE Wideband Encapsulator and Decapsulator IP cores. 

New Website goes online.

Why we exist

Mankind is currently shifting from the industry age to the information age, where information is becoming one of our most important and valuable resources. We at Creonic want to be an active participant in this unique transition. We believe that reliable storage and transmission of vast amounts of digital data are the cornerstones of this new era.

Creonic strives to satisfy the need for reliability and ever increasing data rates with products of the highest quality. We help to fuel modems, data centers, satellites, and more, with the latest algorithms of communications. Our chip designs enable start-ups and global players across the globe to build the equipment of the future.

The Founders

As founders of Creonic we, Dr. Matthias Alles and Dr. Timo Lehnigk-Emden, stand for high quality and state-of-the art products. We offer years of experience in the field of simulation and implementation for ASICs and FPGAs. Our list of selected publications gives a comprehensive overview of Creonic’s achievements.

2001 - 2006 Studies of information technology "with distinction" at University of Kaiserslautern, Germany, reinforcing information processing with main focus on digital circuit design and digital signal processing.
2005 Thesis: "A flexible IRA LDPCC Decoder Architecture for FPGAs".
2006 Diploma thesis: "Synthesisable IP Cores for Irregular LDPC Code Decoding Based on Highly Flexible Architecture Templates".
2006 - 2010 PhD at the research group "Microelectronic Systems Design", University of Kaiserslautern, Germany. Focuses: Implementation of standard-compliant channel decoders for LDPC codes and turbo codes, multi-standard decoder architectures. Contributions to five research and five industry projects.
2006 - 2010 Working as a freelancer in the field of RTL design.
2010 PhD thesis: "Implementation Aspects of Advanced Channel Decoding", grade "with distinction".
since 2010 Managing Partner of Creonic.
1999 - 2005 Studies of electrical engineering at University of Kaiserslautern, Germany, reinforcement of communications technology.
2004 Thesis: "Rekonstruktion der Höhe von topographischen Objekten mit Hilfe der digitalen Bildverarbeitung".
2004 Internship at Alcatel Lucent in Stuttgart, Germany in the field of fiber optic.
2005 Diploma thesis: "LDPC Decoding Algorithms under Quantization Effects".
2010 Internship at Xilinx headquarters in San Jose, California in the field of high-level synthesis for FPGA (AutoESL).
2005 - 2010 Scientific employee at the research group "Microelectronic Systems Design", University of Kaiserslautern, Germany. Focuses: analysis and simulation of non-binary LDPC codes and non-binary turbo codes. Contributions to five research and five industry projects.
2011 PhD thesis: "Implementation and Simulation Aspects of Advanced Non-Binary Iterative Coding Schemes".
since 2010 Managing Partner of Creonic.


Creonic’s designs, such as our IP cores, have to comply with the following rules:


Highest Quality

Highest quality is the primary focus at Creonic. The strict adherence to coding guidelines, utmost verification of the developed circuits, and hardware emulation with FPGA platforms contribute to the quality assurance. Our quality management system is certified according to ISO 9001:2015.

Excellent Performance

During the development of our circuits, performance plays the primary role. The decision for an architecture is only made if it…

  • requires few resources,
  • offers the highest clock frequencies, and
  • consumes little energy.

Simple Handling and Extensive Documentation

Thanks to extensive documentation and easy-to-use interfaces, our products can be easily integrated into your system in no time at all – you will benefit from shorter development times and lower costs!

The Creonic Software Framework

Our primary aim is to offer our customers optimal solutions adhering to timelines and budgets. The design flow for hardware and software components, which was especially developed within the company, significantly contributes to our success. Years of experience and the know-how of our partners have been adopted by the Creonic software framework. Objectives during the development were: 


Shorter development times of IP cores and systems in order to reduce costs.


Simple reuse of single functionalities 
(e.g., of decoder models).


Short test and 
verification times.


High speed of innovation by means of quick adaptation to new communication standards.