Below you can find answers to the questions we get asked the most.


How can we purchase?

The sales team will prepare a quote which you just need to sign. It refers to our standard terms and conditions for IP core licensing. Once this sales order is in place, you may issue a purchase order (PO) that refers to it. However, we do not necessarily need a PO. We reject POs if sent without having a sales order in place.

Typically, the support, maintenance and warranty period is 12 months starting with delivery of the IP core. This can be extended on an annual basis.

We only accept wire transfers. Credit cards or other payment methods are not supported.

Yes, for FPGAs we offer 60 days evaluation licenses against a fee that will be deducted from the purchase price after successful evaluation. Please contact the sales team for more information.

The evaluation license is a 60 days time-limited license. During the evaluation period you are able to receive technical integration support via e-mail and phone. The evaluation license comes as an encrypted netlist that allows you to generate a bitstream in order to test the design on the FPGA. It will stop working after running for a couple of hours within the FPGA. The FPGA needs reprogramming in that case.

After receipt of advance payment, it typically takes five business days for shipping off-the-shelf products. Lead time can be longer in case of IP core customization.

Yes, IP core customization is possible. Pricing is based on the NRE costs involved. Please contact the sales team to check for pricing and lead time.


Creonic is certified according to ISO 9001:2015 (quality management systems). Initial certification was achieved in 2013.

Some products are silicon-proven while others are field-proven based on FPGA technology. If a product is silicon-proven, it will be mentioned on the website and in the datasheet.

The IP cores are developed in a two-step process: First we develop a golden reference model in C++. This reference model is used to carry out performance simulations w.r.t. error rates and ES/N0 performance. Once we are satisfied with the performance, we start writing the RTL code of the IP core. For optimal performance, the RTL code is hand-written without usage of high-level synthesis tools.

All IPs are validated running excessive simulations, comparing the golden reference model in C++ with the RTL model.
We perform constrained random verification, code coverage tests, linting, post-synthesis simulation, and continuous integration. Some IP blocks were also tested on FPGA equipment.

The DVB-S2X cores are running in the lab on various FPGA platforms. The blocks were validated against 3rd party modulators and demodulators as well as real satellite signals. We have multiple customers selling products based on these IP cores. The DVB-S2X decoder is a silicon-proven core. The DVB-S2X modulator operates in many nanosatellites in space.


We provide login credentials for our download server once the deliverable is ready. The download server is located in Germany. Please keep the access data as long as you are under technical support and maintenance. It allows exchanging information (e.g. for trouble shooting) in a bi-directional and secure manner.

After the license agreement is executed and the advance payment is made, it typically takes five business days for shipping off-the-shelf products. Lead time can be longer in case of IP core customization.

The software model comes with a plain C interface. It can be easily used from within your C, C++ or Matlab environment. For Matlab, the loadlibrary command allows usage of the provided library. Typically, the software model comes with an example written in Matlab.

The deliverable typically comes with the IP core in the requested format (netlist, source code), documentation, self-checking VHDL testbench with test vectors, simulation model for your simulator, and the bit-accurate software library with application examples in C++ and Matlab. IP cores with AXI4-Lite interfaces also come with a C++ software firmware that allows working with the IP cores when used in combination with a software processor.

We offer the software models for Linux 64-bit and Windows 64-bit.

Most of our IP cores are written in VHDL language. Please check the deliverables as given on the website, the product brief or the datasheet in order to find out about the RTL language of a specific product.

Yes. Besides selling and customizing IP cores, we also offer integration services, such as developing the design around the IP core, up
to designing the entire internals of the FPGA. This also covers interfaces like Ethernet and JESD204.

Technical Support

Technical support is provided via e-mail or phone directly by Creonic’s engineering staff. The support e-mail address will be made available within the deliverable.

One month before expiration of technical support, maintenance and warranty, we will make an offer for extension. You may send a PO referring to this offer. We will then issue an invoice accordingly.

We try to provide first feedback within one business day. Creonic is located in Germany being in the UTC+1 (CET) or UTC+2 (CEST) time zones.

On-site support is possible against an extra fee. For integration support, Teams sessions are also possible at no extra costs. Typically, our clients prefer this kind of remote debugging instead of on-site support.

Your question is not answered? Just drop our sales team a mail under sales@creonic.com


We are 
ISO 9001:2015

Our customers can rely on consistently high quality, guaranteed by our certified quality management.