The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It uses the 60 GHz band to enable short range communication and interoperability between a broad set of applications and platforms. The Creonic WiGig LDPC decoder is designed in particular to deliver highest throughputs in the multi-gigabit domain with a small footprint. At the same time it provides outstanding error correction performance, resulting in a low energy consumption and increasing range of wireless transmission. Its unique pipeline architecture can be customized at design-time to deliver best performance on any target technology (ASIC technology nodes and FPGAs). Insertion, removal and balancing of pipeline stages within the IP core is flexible and allows for optimization of required routing resources, path delays between pipeline stages, throughput, and footprint at the same time.
Interested? Contact us!
Kevin Christoffers
Director - Business Development & Sales
Product Brief
Download for more information.
- Wireless Local Area Networks (WLAN)
- Ultra-wideband (UWB)
- Microwave Links
- Optical Links
- Further High-throughput Applications
- Compliant with IEEE 802.11ad
- Support for 672 bits codewords and all LDPC code rates (1/2, 5/8, 3/4, 13/16)
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- Silicon-proven IP
- Unique pipeline architecture allows for perfect customization to customer’s target technology
- Gains up to 3 dB compared to Viterbi decoders
- Low-power and low-complexity design.
- Block-to-block on-the-fly configuration.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
- Collection of statistical information (number of iterations, successful decoding)
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for ASIC and FPGAs
