Hardware model as netlist or encrypted source code for Xilinx or Altera FPGAs
Hardware model as VHDL source code
Bit-accurate software reference model as pre-compiled library for Linux or Windows. You can easily integrate this model into your Matlab, C or C++ environment.
Test environment for the hardware of the IP core consisting of VHDL testbench and test data as well as post-synthesis simulation model or pre-compiled simulation model.
Delivery will be made either by download from our FTP server or by encrypted email.
