Creonic Announces DVB-RCS2 Turbo Decoder IP Core
Kaiserslautern, Germany, Aug. 14 2012 – Creonic today announced the availability of the world’s first high-efficiency turbo decoder IP core for DVB-RCS2 for the fourth quarter of 2012. After DVB-RCS, DVB-RCS2 is the second generation DVB standard for interactive satellite systems. The new standard delivers a drastically increased spectral efficiency and higher throughputs compared to its predecessor, hence clearly reducing costs of satellite modem operators.
These improvements are achieved by employment of a new 16-state double-binary turbo code that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes, fulfilling the continuous demand for increased spectral efficiency. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.
The Creonic DVB-RCS2 turbo decoder IP core will be available for ASIC and FPGA technology and can be tailored to different throughput requirements. It furthermore offers a great block length and code rate flexibility beyond the requirements of DVB-RCS2. The IP core embodies the considerable experience of the Creonic experts in turbo decoder design as well as the latest scientific findings from academic studies. It therefore achieves highest clock frequencies and an outstanding area efficiency.
Creonic offers ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The product portfolio covers standards like DVB-S2, DVB-C2, WiFi, UWB, and GMR. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information, please visit www.creonic.com.