The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards.
The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. Finally, it provides the data as baseband frames (BBFRAMEs) to the Creonic DVB-S2/DVB-S2X modulator. The Creonic DVB-GSE decapsulator performs the decapsulation of BBFRAMEs, containing one or more GSE packets. As a last step, it extracts the PDUs, i.e. the network layer packets, from the GSE packets and provides it to the user.
Interested? Contact us!
Kevin Christoffers
Director - Business Development & Sales
Product Brief
Download for more information.
- Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
- Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
- Fragmentation of IP datagrams or other network layer packets over baseband frames (BBFRAMEs) to support ACM
- Support for single stream systems
- Support for VLSNR mode in Narrowband
- Support for 3-byte and 6-byte Labeling and Packet Filtering
- Support for Jumbo Frames
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
-
Applications with the need for encapsulation of IP and other network-layer packets over DVB-S2 or DVB-S2X physical layer frames
- The output of the core perfectly matches the Creonic DVB-S2X modulators both in narrowband (M100 and M400) and wideband (M800) versions
- The input of the core perfectly matches the Creonic DVB-S2(X) Decoders and DVB-S2X Wideband Decoder
- Optional insertion of Frame CRC-32 in the encapsulator
- Low-power and low-complexity design
- AXI4-Stream data interfaces for a seamless integration
- AXI4-Lite interface for configuration and retrieval of status information
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for ASIC and FPGAs
