GEO-Mobile Radio (GMR) LDPC Decoder 


GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time. The same burst modes and LDPC codes are also in GMR Release 3 (GMR-3G). The Creonic GMR LDPC decoder IP core is a field-proven solution.


FLEXIBILITY

LATENCY

THROUGHPUT

ERROR CORRECTION


Interested? Contact us!​

Kevin Christoffers 
Director - Business Development & Sales


Product Brief

Download for more information.


Applications

  • Satellite Telephony
  • Further Low-throughput Applications





  • ​Compliant with GMR Release 2, ETSI TS 101 376-5-3 V2.3.1 (2008-07) (GMPRS-1 05.003)
  • Compliant with GMR Release 3, ETSI TS 101 376-5-3 V3.1.1 (2009-07) (GMR-3G 45.003)
  • Support for return and forward link.
  • Support for short PNB2 (5,3) bursts and long PNB2 (5,12) bursts
  • Support for all PNB2 modulation schemes (Pi/4-QPSK, 16-APSK, 32-APSK)
  • Support for all PNB2 shortening, repeating, and puncturing schemes.
  • Support for all PNB2 LDPC codes (approximate channel coding rates 1/2, 2/3, 4/5, 9/10)

Features

We are ISO 9001:2015 certified

Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

Quality

Benefits

  • FPGA-proven design, validated with satellite data
  • Soft-decision demapper, LLR-descrambler, block deinterleaver, and LDPC decoder included
  • Low-power and low-complexity design
  • Burst-to-burst on-the-fly configuration
  • Design-time configuration of throughput for optimal resource utilization
  • Faster convergence due to layered LDPC decoder architecture
  • Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
  • Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
  • Collection of statistic information (number of modified information bits, number of iterations, decoding successful)
  • The software model includes the corresponding transmitter part
  • Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model  
  • Available for ASIC and FPGAs