IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput. The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
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Kevin Christoffers
Director - Business Development & Sales
Product Brief
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- KR4 single channel
- KP4/200 g single channel
- KP4/KR4 single channel
- KP4/KR4 multi channel
- KP4/KR4/RS272 single channel
- KP4/KR4/RS272 multi channel
- Compliant with IEEE 802.3bj, Clause 91
- Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
- Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbolsCompliant with IEEE 802.3bj, Clause 91
- Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
- Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- High-throughput, low-latency core
- Support for single channel mode (up to 100 Gbit/s)
- Support for bypass mode with low laten
- Symbol error measurement per lane
- Detection of un-correctable code words
- Block-to-block on-the-fly switching between KP4/KR4 codes
- Easy-to-use handshaking interfaces.
- No internal RAM required
- Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation modelDeliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for ASIC and FPGAs
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