ITU 25G PON LDPC 

Encoder and Decoder


The common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks is defined as part of the FEC in the ITU-T G.9804.2 Recommendation.

The Creonic ITU 25G PON LDPC Encoder and Decoder support the default LDPC (17280, 14592) coding scheme, as well as the optional LDPC (17152, 14592) scheme.

  

FLEXIBILITY

LATENCY

THROUGHPUT

ERROR CORRECTION


Interested? Contact us!​

Kevin Christoffers 
Director - Business Development & Sales


Product Brief

Download for more information.


Applications

Quality

  • Passive Optical Networks (e.g. residential, business or mobile backhaul)






  • Support for code rates 38/45 and 57/67
  • Uncoded block size of 14592 bits
  • Compliant with “Higher speed passive optical networks – Common transmission convergence layer specification, Recommended Standard, ITU-T G.9804.2, October 2021”

Features

We are ISO 9001:2015 certified

Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

Benefits

Key benefits of the decoder: 

    • Scalable solution allows for deployment on a wide  range of target technologies
    • Low-power and low-complexity design
    • Layered LDPC decoder architecture for faster convergence behavior
    • Block-to-block on-the-fly configuration
    • Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
    • Optional fixed number of iterations ensuring fixed latency for blocks with the same code rate and block length
    • Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
    • Collection of statistic information (number of iterations, decoding success)


Key benefits of the encoder:

    • Coded throughput of 25.4 Gbit/s at a clock frequency of 300 MHz
    • Low-power and low-complexity design
    • Block-to-block on-the-fly configuration


  • Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model  
  • Available for ASIC and FPGAs