NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically, NCR packets are provided periodically over a continuous DVB-S2 or DVB-S2X link. The receiving user terminal uses the knowledge of the master clock in the system to determine when it is allowed to transmit data in a time-division multiple access (TDMA) system, such as DVB-RCS or DVB-RCS2.
In these TDMA systems, the same frequency band is shared among many terminals, making it mandatory to apply a strict transmission schedule for all terminals. The NCR Processor IP core has two main functionalities:
- NCR tracker
- NCR local clock
The NCR tracker provides a local NCR clock which is frequency- and phase-latched to an incoming DVB-S2/DVB-S2X stream containing NCR information. The absolute phase difference between the NCR tracker and the clock source, e.g., satellite, depends upon the distance to the clock source. The NCR local clock provides a precisely settable NCR source clock provided a local and stable 27 MHz clock and a precise 1 PPS (Pulse Per Second) source are available.
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Kevin Christoffers
Director - Business Development & Sales
Product Brief
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- Configurable PI Controller to compensate for frequency drifts
- Synchronous output clock with external 1PPS input
- Easy integration with Creonic components
- RCS2 return channel slot timing
- Clock distribution endpoints
- Clock reference source
- Low cost replacement for GPS disciplined local oscillator
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- Includes NCR tracker and NCR local clock functionality
Compatible with full range of Creonic IP Cores:
- DVB-S2X Demodulator
- DVB-S2X Decoder
- DVB-S2X Modulator
- DVB-RCS2 Modulator
- Available for ASIC and FPGAs (AMD Xilinx, Intel)
- AXI4-Lite support for configuration and retrieval of status information
- Deliverable includes VHDL source code or synthesized netlist, HDL simulation models, VHDL testbench, and bit-accurate Matlab, C or C++ simulation modelDeliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for ASIC and FPGAs (AMD / Xilinx, Intel / Altera, Microchip)
