Creonic Joins Aldec UNITE™ Partner Programme and Accelerates the Development of its IP Cores with Aldec Linting and Advanced Verification Tools
Basingstoke, United Kingdom – 13th November 2012 – Aldec Europe is pleased to announce that fast-growing, Germany-based IP provider Creonic GmbH, active in the field of wired and wireless communications, has joined Aldec’s UNITE™ Programme as an IP Partner.
As a member of the programme, Creonic guarantees its customers interoperability with Aldec’s EDA tools – most notably Active-HDL™, Riviera-PRO™ and ALINT™> – and will offer precompiled simulation models of its IP cores; which will produce a significant gain in simulation performance.
Dr. Matthias Alles, CEO and co-founder of Creonic, comments: “We use Aldec’s solutions to accelerate the development of our cutting-edge IP cores. For example, ALINT is used heavily for design rule checking and Riviera-PRO is our chosen platform for advanced verification. We’re also a keen advocate of the functional coverage capability within the Open Source VHDL Verification Methodology (OS-VVM™), with which Aldec has strong ties.”
Creonic offers ready-for-use IP cores for many communications algorithms and the company’s areas of expertise include Forward Error Correction (e.g. LDPC and Turbo coding) and synchronization, as well as MIMO and OFDM.
Christina Toole, Corporate Marketing Manager of Aldec Inc., states: “Long-term relationships are the cornerstone of Aldec’s success, and through our UNITE™ Programme we are working with many of the industry’s most well-known vendors of EDA solutions, IP developers and training companies to benefit our mutual customers.”
concludes: “Through our use of Aldec’s EDA solutions and taking
advantage of the OS-VVM we’re able to ensure our IP products comply with
the highest requirements in terms of quality and performance. In
addition, and a most welcome benefit, the UNITE™ programme has opened up
new sales avenues for our IP offerings.”
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
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