CCSDS 131.2 Wideband

Demodulator


The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver. It allows for processing symbol rates of 500 Msymb/s on state-of-the-art FPGAs. The demodulator expects the quantized, complex baseband samples from ananalog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition, the core handles PL frame recovery and PL deframing. The output inter-face of the demodulator perfectly fits the Creonic CCSDS Forward Error Correction IP core that implements a Serial Concatenated Convolutional Code (SCCC) decoding.  

  

FLEXIBILITY

THROUGHPUT

LATENCY


Interested? Contact us!​

Kevin Christoffers 
Director - Business Development & Sales


Product Brief

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Applications

  • Satellite communication
    • High data rate telemetry 
      applications

    • Earth Exploration Satellite 
      Service (EESS)
  • Applications with the highest 
    demands on forward error correction
  • Applications with the need for a wide 
    range of code rates and block lengths






  • ​Compliant with CCSDS 131.2-B-1
  • Supports ACM mode
  • Supports roll-off factors 5%, 10%, 15%, 20%, 25% and 35%
  • Support for blocks with pilots only
  • Support for QPSK to 64-APSK
  • Output of XFECFRAMEs for further  processing by the Creonic FEC Decoder

Features

Quality

We are ISO 9001:2015 certified

Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

Benefits

  • Contains radio interface, decimator, timing recovery, equalizer, frame acquisition, and carrier recovery 
  • Performs and supports DC offset correction, I/Q imbalance correction (optional), decimation (optional), FFT-based blind frequency estimation, coarse frequency estimation, timing recovery, matched filtering, downsampling, frame synchronization, fine frequency correction, coarse and fine phase correction, equalization, PL descrambling, and PL deframing 
  • Low-power and low-complexity design  
  • On-the-fly configuration 
  • Memory mapped interface for controlling the core and for retrieving status information 
  • Very fast synchronization due to different sets of filter coefficients for acquisition and tracking mode  
  • Configurable interrupts and output of synchronization status information  
  • AXI4-Stream handshaking interfaces for seamless integration  
  • Perfectly fits to the Creonic CCSDS SCCC Turbo Decoder
  • Available for ASIC and FPGAs