CCSDS AR4JA LDPC Encoder and Decoder
The CCSDS AR4JA LDPC IP core supports code rates 1/2, 2/3, and 4/5 each with uncoded block sizes of 1024, 4096, and 16384 bits. It was designed particularly for deep space missions, but the excellent error correction performance makes it the ideal fit for additional applications with highest demands on forward error correction.
Near-Earth and Deep-Space communication
- Space link communication
- Microwave links
- Optical links
Further applications with the highest demands on forward error correction
Standard Features the Core Supports
- Uncoded block sizes of 1024, 4096, and 16384 bits
- Code rates of 1/2, 2/3, and 4/5
- Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0-B-3, Blue Book”
- Gains more than 3 dB compared to Viterbi decoders
- Low-power and low-complexity design.
- Layered LDPC decoder architecture, for faster convergence behavior
- Block-to-block on-the-fly configuration.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
- Collection of statistic information (number of iterations, decoding success, number of modified bits)
- Available for ASIC and FPGAs (Xilinx, Intel, Microchip)
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
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