CCSDS LDPC 

Encoder and Decoder


The Creonic CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard. The LDPC code with single rate 223/255 was specifically designed for Near-Earth missions, but the excellent error correction performance also makes it an ideal solution for a wide variety of high-throughput applications.  

  

FLEXIBILITY

LATENCY

THROUGHPUT

ERROR CORRECTION


Interested? Contact us!​

Kevin Christoffers 
Director - Business Development & Sales


Product Brief

Download for more information.


Applications

Features

  • Near-Earth and Deep-Space communication
  • Space links communication
  • Space internetworking services
  • Microwave Links
  • Optical Links
  • Further High-throughput Application






  • Support for code rate 223/255 (7136/8160) 
  • Coded block size 8160 bits  
  • Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0 B-3, Blue Book, September 2017” ​
We are ISO 9001:2015 certified

Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

Quality

Benefits

Key benefits of the decoder: 

    • Gains of up to 3 dB compared to Viterbi decoders 
    • Low-power and low-complexity design 
    •  Layered LDPC decoder architecture, for convergence behavior that is twice as fast as non-layered LDPC decoders 
    • Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance 
    • Collection of statistic information (number of iterations, decoding success) Collection of statistic information (number of iterations, decoding success)   


Key benefits of the encoder:

    • High-throughput, low-latency encoder core 
    • Low-power and low-complexity design 
    • No BRAM required   


  • Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model  
  • Available for ASIC and FPGAs