DVB-S2X LDPC / BCH
Decoder

The Creonic DVB-S2X decoder IP core is a scalable solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FPGAs. DVB-S2X is the next generation satellite transmission standard which is an extended version of its well-established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.

PRODUCT BRIEF

FLEXIBILITY

LATENCY

THROUGHPUT

ERROR CORRECTION

Applications

Satellite communication (Digital Video Broadcasting, Interactive Services, News Gathering, Professional Services)
Nanosatellite and CubeSat devices
Applications with the highest demands on forward error correction
Applications with the need for a wide range of code rates

Standard Features the Core Supports

Compliant with ETSI EN 302 307-1 V1.4.1 (2014-11) (DVB-S2) and ETSI EN 302 307-2 V1.1.1 (2014-10) (DVB-S2X).
Supports ACM, CCM, and VCM modes
Support for short, medium and long blocks (16200, 32400 and 64800 bits).
Support for all modulation schemes (BPSK, QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK, 128-APSK, 256-APSK)
Support for very low SNR modes (VLSNR) with SNRs below -9 dB.
Support for all LDPC and BCH codes as defined by the standard

Your Benefits

Validated against 3rd party DVB-S2X modulators
Based on industry-proven design for DVB-S2
Decoder contains soft-decision demapper, block deinterleaver, LDPC decoder, BCH decoder, and descrambler.
Low-power and low-complexity design
Burst-to-burst on-the-fly configuration
Faster convergence due to layered LDPC decoder architecture.
Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy

Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
Collection of statistics (decoding success indicator, average number of iterations)
Available for ASIC and FPGAs (Xilinx, Intel, Microchip)
Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model