Creonic Unveils 100 Gbit/s IEEE 802.3bj Reed-Solomon FEC IP Cores
Kaiserslautern, Germany, Jan. 5 2015 – Creonic today announced the immediate availability of its Reed-Solomon Encoder and Decoder IP cores according to the IEEE 802.3bj standard. The IP cores are characterized by processing 160 bits per clock cycle, resulting in throughputs of 100 Gbit/s on ASIC technologies. Even on state-of-the-art FPGAs throughputs beyond 30 Gbit/s are feasible with a single core. Additionally, the IP cores provide extremely low decoding latencies of less than 100 ns and small footprint.
“Our latest IP core is not only suitable for 100 Gbit Ethernet but also for FPGA-based applications in the backhaul market. We are particularly pleased that Creonic has already sold multiple licenses of the IP core”, said Dr. Matthias Alles, CEO and co-founder of Creonic.
During operation the decoder measures the error rate. In the case of an optimal link the decoder can operate in bypass mode in order to further reduce the latency. Overall a code word consists of 528 symbols comprising 10 bits each. The Reed-Solomon code can correct up to seven symbols. Deliveries of the IP core are Verilog/VHDL source code or netlist, a bit accurate software model for C/C++/Matlab environments as well as a VHDL testbench.
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