Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1
Kaiserslautern, Germany, Oct. 28, 2015 – Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 technology consists of the newest and first-rate of digital communication technologies such as LDPC coding with very high modulation orders (up to 4096-QAM) and more than 1 GHz of usable spectrum. It therefore supports speeds of up to 10 Gbps in downstream and 1 Gbps in upstream.
Creonic offers three LDPC decoder IP cores for the downstream of DOCSIS 3.1. The first decoder takes care of the physical link layer channel (PLC). It comprises 16-QAM demapper, derandomizer, deinterleaver and LDPC decoder. The second decoder performs decoding of the next codeword pointer (NCP) and comprises QPSK/16-QAM/64-QAM demapper, derandomizer and LDPC decoder. The third decoder is responsible for the data path and comprises LDPC and BCH decoder including support for shortening. It offers throughputs beyond 2.3 Gbps on state-of-the-art FPGAs and provides an outstanding area efficiency.
The IP cores are available for FPGA and ASIC platforms either as un-encrypted or encrypted source code. They come with HDL simulation models, VHDL testbench and comprehensive documentation. Furthermore, bit-accurate software models for usage in customer’s own C/C++/Matlab simulation environments are available.
Learn more about the Creonic DOCSIS 3.1 LDPC IP Core
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