The Creonic DVB-S2X Wideband Modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4 Gbit/s for 256-APSK) on state-of-the-art FPGAs. The IP core performs all tasks of the inner transmitter and complements the Creonic DVB-S2X Wideband Receiver Solutions (DVB-S2X Wideband Demodulator and DVB-S2X LDPC/BCH Wideband Decoder). The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition, the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.
DVB-S2X is the next generation satellite transmission standard which is an extended version of its well-established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.
Interested? Contact us!
Kevin Christoffers
Director - Business Development & Sales
Product Brief
Download for more information.
- Satellite communication
- Digital Video Broadcasting
- Interactive Services
- News Gathering
- Professional Services
- Compliant with DVB-S2 and DVB-S2X
- Supports ACM, CCM, and VCM modes
- Support for short and normal frames (16,200 bits and 64,800 bits)
- Support for QPSK to 256-APSK
- VLSNR modes on request
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- Validated against the field-proven Creonic DVB-S2X Demodulator and Decoder IP cores
- Easy-to-use mode adaptation input interface
- Provides interpolated and gain-adjusted ZF basebend signal
- The modulator contains padder, BB scrambler, BCH encoder, LDPC encoder, bit interleaver, bit mapper, dummy PL frame insertion, PL signalling, pilot insertion, PL scrambler, baseband filter, interpolator, and gain adjustment
- Can be complemented with the Creonic DVB-CID Modulator
- Low-power and low-complexity design
- Memory-mapped interface for controlling and for retrieving status information
- Flexible output interface, which can be driven by an external clock for easy synchronization with DAC
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for FPGAs and ASICs (AMD / Xilinx, Intel / Altera, Microchip)
