Creonic to Provide Full DVB-S2X Transmitter and Receiver IP Core Solution
Kaiserslautern, Germany, Feb. 22, 2016 – Creonic GmbH, a leading IP core provider for communications, announced today the release of the new DVB-S2X modulator IP core. The modulator core is the last piece and completes Creonic’s field-proven IP core portfolio for DVB-S2X, namely receiver (demodulator and LDPC/BCH FEC decoder), LDPC/BCH FEC encoder, and DVB-CID modulator. Customers no longer have to bother looking for individual components from different vendors since it is now possible to get transmitter and receiver from one source.
The DVB-S2X modulator achieves symbol rates of up to 250 Msymbols/s on FPGAs for all supported modulations (QPSK up to 256-APSK) resulting in throughputs of 2 Gbit/s for 256-APSK. It supports short and normal frames (16,200 bits and 64,800 bits) as well as CCM, ACM and VCM modes. The core is equipped with an easy-to-use mode adaptation input interface. On the output side it provides an interpolated and gain adjustable ZF baseband signal. The core comes with an optional DVB-CID modulator license.
Even though the DVB-S2X standard is meant for satellite communication in the first place, the unique properties of the IP cores make them the ideal fit for further applications with high throughput and flexibility requirements.
The IP cores are available for ASIC and FPGA (Xilinx and Altera) technologies either as plain or encrypted source code. In addition, the cores come with HDL simulation models, self-checking testbench, bit-accurate Matlab, C or C++ simulation model and comprehensive documentation.